1. Field of the Invention
The present invention relates to a method of production of a circuit board used for a semiconductor device etc., more particularly relates to a method of production of a circuit board not requiring power feed plating interconnects when producing a circuit board utilizing electroplating.
2. Description of the Related Art
In the past, when producing circuit boards used for semiconductor devices, for example, a large board 1 comprised of a glass prepreg or other resin as shown in FIG. 1A was prepared, this large board 1 was formed with circuit patterns 5 corresponding to a plurality of circuit boards 3 in a matrix, then this was cut along predetermined cutting lines 7 so as to obtain the individual circuit boards 3.
In particular, when using the subtractive method (tenting method) to form circuit patterns on the large board 1, since the bonding pads and other main parts of the circuit patterns 5 are electroplated for nickel plating or gold plating, power feed plating interconnects 9 for short-circuiting between circuit patterns are provided outside of the circuit boards 3 obtained by the cutting. Note that FIG. 1B shows enlarged parts of the circuit patterns 5 and plating interconnects 9 shown in FIG. 1A, wherein 11 shows bonding pads and 13 shows through holes.
When electroplating, the large board 1 is immersed in a plating solution (not shown) and plating interconnects 9 at the outer circumference of the large board 1 are connected to plating electrodes (not shown) so as to feed power to the circuit patterns 5 and electroplate the necessary locations of the circuit patterns 5 with nickel or gold.
After the electroplating, the large board 1 is cut at the inside parts of the plating interconnects 9 (parts along cutting lines 7 shown by broken lines) to obtain the individual circuit boards 3. For this reason, the circuit patterns 5 of the circuit boards 3 have parts 15 required only for connection to the plating interconnects 9 and not required for transmission of electric signals etc. from the through holes 13 to the outer edges of the circuit boards 3.
As such a circuit board 3, there is one used for a semiconductor device called a BGA (Ball Grid Array). In FIGS. 2A to 2K, a method of production of a circuit board obtained by the conventional subtractive method, in particular a circuit board 3 used for a BGA, will be explained step by step. Further, a BGA using a circuit board 3 produced in this way is shown in FIG. 3A. Note that the drawings of FIGS. 2A to 2K show a method of production of a circuit pattern of the sectional part shown by X in FIG. 3A (circuit pattern formation method).
In FIG. 2A, first a large double-sided copper-clad multilayer board 10 comprised of a resin board (glass prepreg) 1 clad with copper foil 17, 17 on its two surfaces is prepared. This double-sided copper-clad multilayer board 10 is formed on its surfaces with a plurality of circuit boards 3 as shown in FIG. 1A.
In FIG. 2B, a drill (not shown) is used to form through holes 13 at required locations.
In FIG. 2C, the entire surface including the inside walls of the through holes 13 is given a copper or other electroless plating 19.
In FIG. 2D, power is fed from the electroless plating layer 19 to give the electroless plating layer 19 a copper or other electroplating 21. Due to this, a plating thickness required for formation of the circuit patterns is formed.
In FIG. 2E, the electroplating layer 21 is coated with a film-like etching resist called a “dry film resist”. This is exposed and developed to form resist patterns 23 corresponding to predetermined circuit patterns.
In FIG. 2F, the resist patterns 23 are used as masks for etching so as to remove parts of the copper electroplating layer 21, copper electroless plating layer 19, and copper foil 17 exposed from the resist patterns 23 and unnecessary for formation of circuit patterns and thereby form the circuit patterns 5.
In FIG. 2G, the resist patterns 23 are removed. Due to this, the circuit patterns 5 are exposed. The circuit patterns 5 are connected through connection parts 5c to the plating interconnects 9 formed simultaneously with the circuit patterns 5 and are short-circuited from each other as shown in FIGS. 1A and 1B. Note that these plating interconnects 9, as shown in FIGS. 1A and 1B, are formed on the large resin board 1 in frame shapes outside of cutting lines 7 for obtaining the plurality of circuit boards 3 and before cutting are connected to all of the circuit patterns 5 of the circuit boards 3.
Next, in FIG. 2H, a solder resist is coated by printing and exposed and developed to form solder resist patterns 25. At this time, the solder resist patterns 25 are formed so that the bonding pads 11 of the circuit patterns 5, the external connection pads (parts for connection with solder balls) 31, and other required locations are exposed.
In FIG. 2I, power is fed from the plating interconnects 9 (FIGS. 1A and 1B) to give the wire bonding pads 11 and external connection pads 31 nickel electroplating 27, then gold electroplating 29. Note that FIG. 2J is a view seen from above FIG. 3B (however, solder resist patterns 25 not shown). As illustrated, at the time of nickel/gold (Ni/Au) electroplating, the circuit patterns 5 are short-circuited by the plating interconnects 9.
In FIG. 2K, the large board 1 is cut along the cutting lines 7 shown by FIGS. 2I and 2J to obtain the individual circuit boards 3.
After this, a semiconductor chip 33 is mounted on each of the circuit boards 3, bonding wires 35 are used to connect the semiconductor chip 33 and wire bonding pads 11, a resin 37 is used to seal them, then solder balls 39 are joined to thereby obtain a semiconductor device (BGA) as shown in FIG. 3A. FIG. 3B is a view of the part of the circuit board shown by X in FIG. 3A seen from above (state with sealing resin 37 and solder resist patterns 25 removed). The semiconductor chip 33 may otherwise be mounted on each of the circuit boards 3 by flip chip bonding, where the circuit boards 3 have pads to be connected to bumps of the semiconductor chip 33. The circuit board 3 may be any of BGA (ball grid array), LGA (lad grid array) and PGA (pin grid array). An LGA has pads functioning as an external connection terminal in themselves. A PGA has pins which, instead of solder balls, are connected to external connection pads.
If using a circuit board 3 shown in FIG. 3A produced by the above conventional subtractive method, as shown in FIG. 3B, the circuit pattern 5 is formed with unnecessary parts (parts 5c connecting to plating interconnects) extending from the parts of the through holes 13 to the outer edges 7a of the cut circuit board 3. These unnecessary parts 5c cause signal reflection and noise and degrade the electrical properties of the semiconductor device. Further, if providing such plating interconnects 9 and connecting parts 5c, the layout of the circuit patterns 5 is restricted by the amount of the plating interconnects 9 and connecting parts 5c, so higher density of the circuit patterns 5 is inhibited.
Note that as prior art relating to the present invention, there is Japanese Patent Publication (A) No. 2000-114412. This discloses improving the bonding between the circuit patterns and board, enabling finer circuit patterns, and improving the bonding between the solder resist and conductor parts by using a copper layer formed on the board surface as a power feed layer for electroplating and by etching the copper layer using resist patterns as masks so as to form circuit patterns.